1. Field of the Invention
The present invention relates to a BTL (balanced transformer-less) amplifier and more particularly, to offset voltage compensation of the BTL amplifier.
2. Description of the Background Art
In an amplifier system called BTL (balanced transformer-less), two amplifier circuits are actuated in reverse phase with the aim of obtaining the output between their respective output terminals that is double in amplitude the output obtained when these amplifier circuits are used singly. An amplifier using such a system is called as a BTL amplifier, an example of which is introduced in Japanese Patent Application Laid-Open No. 5-335850 (1993) (pages 2–3 and FIGS. 1–3), for example.
An operational amplifier constituting the BTL amplifier generally comprises a transistor pair such as a differential pair circuit or a current mirror circuit, whose operating characteristic has great dependence on match in electrical characteristic between the transistors as a pair. When the input voltage of the operational amplifier is set to zero, the output voltage should also ideally be zero. However, a nonzero output voltage is produced due to mismatch in characteristic between the transistors as a pair that form the operational amplifier, for example, which means generation of an output offset voltage which is the voltage appearing on the output when the input voltage is set to zero.
For cost reduction of ICs, use of MOS devices as semiconductor device structures has been promoted. However, MOS transistors exhibit a wider range of variation in electrical characteristic than bipolar transistors. The operational amplifier using a pair of MOS transistors is thus likely to generate an output offset voltage and an input offset voltage (the voltage to give a zero output voltage). Accordingly, when the operational amplifier as a constituent of the BTL amplifier uses a pair of MOS transistors for cost reduction, the BTL amplifier may generate an offset voltage. Generation of an offset voltage may adversely affect a post-stage circuit of the BTL amplifier, or may generate unintended current flow through a load in a no-signal stage.
Techniques such as zapping in outgoing inspection, use of an offset canceller by means of a capacitor, calibration for offset voltage compensation in a system as a whole comprising MOS devices, and the like, are responsive to suppression of generation of an offset voltage in MOS transistors. Zapping in outgoing inspection increases inspection cost and causes chip size increase, thus inhibiting cost reduction as an advantage of MOS devices. Use of an offset canceller by means of a capacitor encounters a difficulty in maintaining the amount of trimming with stability, and hence, is not suitably applied in MOS devices operating under severe conditions such as high temperature, large current and negative voltage. In order to realize cost reduction while providing stable compensation of an offset voltage, calibration in a system as a whole is effectively applicable.